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CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committee

Scope

The 3D-TEST Workshop focuses exclusively on test of and design-for-test for three-dimensional stacked ICs (3D-SICs), including Systems-in-Package (SiP), Package-on-Package (PoP), and especially 3D-SICs based on Through-Silicon Vias (TSVs), microbumps, and/or interposers. While 3D-SICs offer many attractive advantages with respect to heterogeneous integration, smaller form-factor, higher bandwidth and performance, and lower power dissipation, there are many open issues with respect to testing such products. The 3D-TEST Workshop offers a forum to present and discuss these challenges and (emerging) solutions among researchers and practitioners alike.

3D-TEST will take place in conjunction with the IEEE International Test Conference (ITC) and is sponsored by the Test Technology Technical Council (TTTC) of IEEE Computer Society.

Topic Areas � You are invited to participate and submit your contributions to the 3D-TEST Workshop. The workshop�s areas of interest include (but are not limited to) the following topics:

Defects due to Wafer Thinning
Defects in Intra-Stack Interconnects
DfT Architectures for 3D-SICs
EDA Design-to-Test Flow for 3D-SICs
Failure Analysis for 3D-SICs
Fault-Tolerant Design for 3D-SICs
Interposer Testing
Known-Good Die / Stack Testing
Power and Heat Dissipation during Test
Pre-Bond, Mid-Bond and Post-Bond Test
Reliability of 3D-SICs
Stacking Yield of Dies and Interconnects
Standardization for 3D Testing
System/Board Test Issues for 3D-SICs
Test Cost Modeling for 3D-SICs
Test Flow Optimization for 3D-SICs
Tester Architecture incl. ATE and BIST
Thermal/Mechanical Stress in 3D-SICs
TSV Test, Redundancy, and Repair
Wafer Probing and Probe Marks of 3D-SICs

Submissions

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Submissions must be sent in as PDF file. The Workshop prefers Full Paper submissions (of up to six pages), but also allows Extended Abstract submissions (of at least two pages). Detailed submission instructions can be found at the Workshop�s website: http://3dtest.tttc-events.org. All submissions will be evaluated for selection with respect to their suitability for the workshop, originality, technical soundness, and presented results. Selected submissions can be accepted for regular or poster presentation at the Workshop.

It is also not yet too late to sign up with your company for (1) a table-top demo and/or (2) corporate support.

The workshop will make available to all participants an Electronic Workshop Digest, which includes all material that authors are willing to provide: abstract, paper, slides, poster, etc.

Key Dates

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Submission deadline: September 17, 2014 (EXTENDED)

Notification of acceptance: September 22, 2014

Camera-ready material: October 6, 2014

Additional Information

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Yervant Zorian � General Chair

Synopsys

700 East Middlefield Road

Mountain View, CA 94043-4033, USA

Tel.: +1 (650) 584-7120

E-mail: yervant.zorian@synopsys.com

Erik Jan Marinissen � Program Chair

IMEC

Kapeldreef 75

B-3001 Leuven, Belgium

Tel.: +32 (0)16 28-8755

E-mail: erik.jan.marinissen@imec.be

Committee

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General Chair:

Y. Zorian � Synopsys (US)

Program Chair:

E.J. Marinissen � IMEC (BE)

Finance Chair:

B. Eklow � Cisco Systems (US)

Finance Vice-Chair / Arrangements:

J. Potter � ASSET InterTech (US)

Publicity Chair:

F. von Trapp � 3DInCites (US)

Publication Chair:

L. Ciganda � Politecnico di Torino (IT)

Web Chair:

G. Jervan � Tallinn Univ. of Techn. (EE)

Program Committee Members:

S. Adham � TSMC (CAN)
V. Agrawal � Auburn Univ. (US)
S. Bhatia � Google (US)
K. Chakrabarty � Duke Univ. (US)
S. Chakravarty � Avago Tech (US)
K.Y. Chung � Samsung (KR)
C.J. Clark � Intellitech (US)
E. Cormack � DfT Solutions (UK)
A. Cron � Synopsys (US)
A. Crouch � ASSET InterTech (US)
D. Domke � Texas Instruments (US)
M.-L. Flottes � LIRMM (FR)
P. Franzon � NC State Univ. (US)
S.K. Goel � TSMC (US)
S. Hamdioui � TU Delft (NL)
M. Higgins � Analog Devices (IRL)
C.-L. Hsu � ITRI (TW)
S.-Y. Huang � NTHU (TW)
M. Hutner � Teradyne (CAN)
H. Jun � SK hynix (KR)
S. Kameyama � Fujitsu (JP)
M. Knox � IBM (US)
M. Laisne � Qualcomm (US)
S. Lecomte � Intel (DE)
K.H. Lee � GigaLane (KR)
C.M. Li � NTU (TW)
M. Loranger � FormFactor (US)
A. Majumdar � Xilinx (US)
T.M. Mak � GlobalFoundries (US)
T. McLaurin � ARM (US)
B. Nadeau-Dostie � Mentor Graph. (US)
C. Papameletis � Cadence (US)
B. Patti � Tezzaron Semiconductor (US)
M. Ricchetti � AMD (US)
S. Shaikh � Broadcom (US)
T. Th�rigen � Cascade Microtech (DE)
P. Vivet � CEA-Leti (FR)
M. Wahl � Univ. Siegen (DE)
Q. Xu � Chinese Univ. Hong Kong (HK)

For more information, visit us on the web at: http://3dtest.tttc-events.org

3D-TEST'15 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).